Microsoft+Hyper-V 源代码

module add4_3(cout,sum,a,b,cin); output[3:0] sum; output cout; input[3:0] a,b; input cin; reg[3:0] sum; reg cout; always …

module half_add4(a,b,sum,cout); input a,b; output sum,cout; reg sum,cout; always @(a or b) begin sum= a^b; cout=a&b; end…

module half_add3(a,b,sum,cout); input a,b; output sum,cout; reg sum,cout; always @(a or b) begin case ({a,b}) …

module full_add4(a,b,cin,sum,cout); input a,b,cin; output sum,cout; reg sum,cout; reg m1,m2,m3; always @(a or b or cin) be…

module add4_2(cout,sum,a,b,cin); output[3:0] sum; output cout; input[3:0] a,b; input cin; assign {cout,sum}=a+b+cin; endmodu…

module full_add3(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign {cout,sum}=a+b+cin; endmodule

primitive mux31(Y,in0,in1,in2,s2,s1); input in0,in1,in2,s2,s1; output Y; table //in0 in1 in2 s2 s1 : Y 0 ? ? 0 0 : …

primitive carry_udpx2(cout,cin,a,b); input cin,a,b; output cout; table // cin a b : cout ? 0 0 : 0; 0 ? 0 : …

'timescale 1ns/1ns module test1; reg A,B,C; initial begin A = 0; B = 1; C = 0; #100 C = 1; #100 A = 1; B = 0; #100 A…

module test2; reg clk1,clk2; parameter CYCLE = 100; always begin {clk1,clk2} = 2'b10; #(CYCLE/4) {clk1,clk2} …