module block3(Q0,Q1,Q2,Q3,din,clk); output Q0,Q1,Q2,Q3; input clk,din; reg Q0,Q1,Q2,Q3; always @(posedge clk) begin …
Microsoft+Hyper-V 源代码
汇集 Microsoft+Hyper-V 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
module adder8(cout,sum,ina,inb,cin,clk); output[7:0] sum; output cout; input[7:0] ina,inb; input cin,clk; reg[7:0] tempa,temp…
module reg8(qout,in,clk,clear); output[7:0] qout; input[7:0] in; input clk,clear; reg[7:0] qout; always @(posedge clk or pose…
module add8(sum,cout,b,a,cin); output[7:0] sum; output cout; input[7:0] a,b; input cin; assign {cout,sum}=a+b+cin; endmodule
module mult4x4(out,a,b,clk); output[7:0] out; input[3:0] a,b; input clk; reg[7:0] out; reg[1:0] firsta,firstb; reg[1:0] seco…
module decoder2(c,y,clk); output[6:0] c; input[6:0] y; input clk; reg[6:0] c,c_buf,buffer; reg temp; reg s0,s1,s2; reg e; …
module count4(out,reset,clk); output[3:0] out; input reset,clk; reg[3:0] out; always @(posedge clk) begin if (reset) out
module adder4(cout,sum,ina,inb,cin); output[3:0] sum; output cout; input[3:0] ina,inb; input cin; assign {cout,sum}=ina+inb+c…