module loop1; integer i; initial for(i=0;i
Microsoft+Hyper-V 源代码
汇集 Microsoft+Hyper-V 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
module decode4_7(decodeout,indec); output[6:0] decodeout; input[3:0] indec; reg[6:0] decodeout; always @(indec) begin …
module MUX21_1(out,a,b,sel); input a,b,sel; output out; assign out=(sel==0)?a:b; endmodule
`timescale 10ns/1ns module wave1; reg wave; parameter cycle=10; initial begin wave=0; #(cycle/2) wave=1; #(…
module mux4_1(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input[1:0] sel; reg out; always @(in0 or in1 or in…
module loop2; integer i; initial begin i=0; while(i
module loop3; integer i; initial begin i=0; repeat(4) begin $display ("i=%h",i); i=i+1; end end endmodule
module MUX21_2(out,a,b,sel); input a,b,sel; output out; reg out; always@(a or b or sel) begin if(sel==0) out=a; …
module paral1(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin q=~q; end always @(posedge clk) b…
module code_83(din,dout); input[7:0] din; output[2:0] dout; function[2:0] code; input[7:0] din; casex (din) 8'b1xxx_xxxx :…