Microsoft+Hyper-V 源代码

module gate1(F,A,B,C,D); input A,B,C,D; output F; nand(F1,A,B); and(F2,B,C,D); or(F,F1,F2); endmodule

module decode47(a,b,c,d,e,f,g,D3,D2,D1,D0); output a,b,c,d,e,f,g; input D3,D2,D1,D0; reg a,b,c,d,e,f,g; always @(D3 or D2 or…

module bidir2(bidir,en,clk); inout[7:0] bidir; input en,clk; reg[7:0] temp; assign bidir= en ? temp : 8'bz; always @(posedge …

module ram256x8(data,address,we,inclock,outclock,q); input[7:0] data; input[7:0] address; input we,inclock,outclock; output[7:…

module latch_8(qout,data,clk); output[7:0] qout; input[7:0] data; input clk; reg[7:0] qout; always @(clk or data) begin i…

module reg8(out_data,in_data,clk,clr); output[7:0] out_data; input[7:0] in_data; input clk,clr; reg[7:0] out_data; always @…

`include "adder.v" module adder16(cout,sum,a,b,cin); output cout; parameter my_size=16; output[my_size-1:0] sum; input[my_s…

`timescale 10ns/1ns module wave2; reg wave; parameter cycle=5; initial fork wave=0; #(cycle) wave=1; #(2*cycle)…

module voter7(pass,vote); output pass; input[6:0] vote; reg[2:0] sum; integer i; reg pass; always @(vote) begin sum=0; …

module count60(qout,cout,data,load,cin,reset,clk); output[7:0] qout; output cout; input[7:0] data; input load,cin,clk,reset; …