Microsoft+Hyper-V 源代码

module serial2(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin a=~q; q=~q; end endmodule

module paral2(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin a=~q; end always @(posedge clk) b…

module serial1(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin q=~q; a=~q; end endmodule

module full_add5(a,b,cin,sum,cout); input a,b,cin; output sum,cout; reg cout,m1,m2,m3; //在always块中被赋值的变量应定义为reg型 wire…

module count4(clk,clr,out); input clk,clr; output[3:0] out; reg[3:0] out; always @(posedge clk or posedge clr) begin if (c…

`include "full_add1.v" module add4_1(sum,cout,a,b,cin); output[3:0] sum; output cout; input[3:0] a,b; input cin; full_add1…

module full_add2(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum = a ^ b ^ cin; assign cout = (a & b)|(b & cin…

module half_add2(a,b,sum,cout); input a,b; output sum,cout; assign sum=a^b; assign cout=a&b; endmodule

module half_add1(a,b,sum,cout); input a,b; output sum,cout; and (cout,a,b); xor (sum,a,b); endmodule

module full_add1(a,b,cin,sum,cout); input a,b,cin; output sum,cout; wire s1,m1,m2,m3; and (m1,a,b), (m2,b,cin), (m…