代码搜索：verilog hdl 是什么？

找到约 10,000 项符合「verilog hdl 是什么？」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/179893/9332298

rpt protect.rpt

Project Informationc:\software\project_beijing\cpld_v1.1\pwm_verilog hdl_v1.1\protect.rpt MAX+plus II Compiler Report File Version 10.1 06/12/2001 Compiled: 03/06/2006 17:15:12 Copyright (C) 1
·
www.eeworm.com/read/179893/9332343

rpt filter.rpt

Project Informationc:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\filter.rpt MAX+plus II Compiler Report File Version 10.1 06/12/2001 Compiled: 03/17/2006 16:26:27 Copyrigh
·
www.eeworm.com/read/18563/794271

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
·
www.eeworm.com/read/343627/3218952

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
·
www.eeworm.com/read/154076/5643171

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
·
www.eeworm.com/read/235010/14088995

ant test_ddr_command.ant

// F:\ISE_TEST // Verilog Annotation Test Bench created by // HDL Bencher 6.1i // Tue Aug 14 10:56:43 2007 `timescale 1ns/1ns `define FDEPTH 4 `define C_READ 5 `define D 10 `define IF2 3
·
www.eeworm.com/read/427635/1968800

srm sdr_sdram.srm

f "noname"; #file 0 f "g:\hdl_doc\ip\sdram\source\command.v"; #file 1 f "g:\hdl_doc\ip\sdram\source\params.v"; #file 2 f "g:\hdl_doc\ip\sdram\source\control_interface.v"; #file 3 f "g:\hdl_doc\ip\
·
www.eeworm.com/read/185226/9049506

log __projnav.log

Project Navigator Auto-Make Log File ------------------------------------- Started process "Compile HDL Simulation Libraries". Process "Compile HDL Simulation Libraries" did not complete.
·
www.eeworm.com/read/290116/8503939

qsf de2_i2sound.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
·
www.eeworm.com/read/431720/8659880

rpt kit_de2.asm.rpt

Assembler report for kit_DE2 Sat May 31 20:22:41 2008 Version 6.0 Build 178 04/27/2006 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2
·