test_ddr_command.ant

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

// F:\ISE_TEST
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Tue Aug 14 10:56:43 2007

`timescale 1ns/1ns

`define FDEPTH	4
`define C_READ	5
`define D	10
`define IF2	3
`define TCKO	0
`define C_L_MODE	0
`define Q	25
`define IF0	1
`define s3	3
`define IF1	2
`define s2	2
`define C_WRITE	4
`define s0	0
`define N	5
`define C_REFRSH	1
`define C_P_CHRG	2
`define C_NOP	7
`define BR0	0
`define F_ASSERT	2
`define C_ACTIVE	3
`define FWIDTH	32
`define FCWIDTH	2
`define F_DEASSERT	4
`define state_delay	6
`define F_IDLE	1
`define OD	4
`define s0	0
`define s1	1
`define RES	5
`define C_L_MODE	0
`define FWIDTH	32
`define RES	5
`define IF1	2
`define IF1	2
`define FWIDTH	32
`define IF1	2
`define IF1	2
`define FCWIDTH	2
`define s3	3
`define s4	4
`define s2	2
`define F_DEASSERT	4
`define s2	2
`define s2	2
`define F_DEASSERT	4
`define C_ACTIVE	3
`define C_L_MODE	0
`define C_L_MODE	0
`define RES	5
`define D	10
`define F_DEASSERT	4
`define C_ACTIVE	3
`define C_NOP	7
`define RES	5
`define IF2	3
`define D	10
`define C_ACTIVE	3
`define F_IDLE	1
`define F_ASSERT	2
`define Q	25
`define N	5

module test_ddr_command;
	reg CLK;
	reg RESET_N;
	reg [21:0] SADDR;
	reg NOP;
	reg READA;
	reg WRITEA;
	reg REFRESH;
	reg PRECHARGE;
	reg LOAD_MODE;
	reg [1:0] SC_CL;
	reg [1:0] SC_RC;
	reg [3:0] SC_RRD;
	reg SC_PM;
	reg [3:0] SC_BL;
	reg REF_REQ;
	wire REF_ACK;
	wire CM_ACK;
	wire OE;
	wire [11:0] SA;
	wire [1:0] BA;
	wire [1:0] CS_N;
	wire CKE;
	wire RAS_N;
	wire CAS_N;
	wire WE_N;
	wire do_nop;
	wire do_reada;
	wire do_writea;
	wire do_refresh;
	wire do_precharge;
	wire do_load_mode;

	ddr_command UUT (
		.CLK(CLK),
		.RESET_N(RESET_N),
		.SADDR(SADDR),
		.NOP(NOP),
		.READA(READA),
		.WRITEA(WRITEA),
		.REFRESH(REFRESH),
		.PRECHARGE(PRECHARGE),
		.LOAD_MODE(LOAD_MODE),
		.SC_CL(SC_CL),
		.SC_RC(SC_RC),
		.SC_RRD(SC_RRD),
		.SC_PM(SC_PM),
		.SC_BL(SC_BL),
		.REF_REQ(REF_REQ),
		.REF_ACK(REF_ACK),
		.CM_ACK(CM_ACK),
		.OE(OE),
		.SA(SA),
		.BA(BA),
		.CS_N(CS_N),
		.CKE(CKE),
		.RAS_N(RAS_N),
		.CAS_N(CAS_N),
		.WE_N(WE_N),
		.do_nop(do_nop),
		.do_reada(do_reada),
		.do_writea(do_writea),
		.do_refresh(do_refresh),
		.do_precharge(do_precharge),
		.do_load_mode(do_load_mode)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	CLK = 1'b0;
	#10
	CLK = 1'b1;
	#10
	ANNOTATE_REF_ACK;
	ANNOTATE_CM_ACK;
	ANNOTATE_OE;
	ANNOTATE_SA;
	ANNOTATE_BA;
	ANNOTATE_CS_N;
	ANNOTATE_CKE;
	ANNOTATE_RAS_N;
	ANNOTATE_CAS_N;
	ANNOTATE_WE_N;
	ANNOTATE_do_nop;
	ANNOTATE_do_reada;
	ANNOTATE_do_writea;
	ANNOTATE_do_refresh;
	ANNOTATE_do_precharge;
	ANNOTATE_do_load_mode;
	#40
	CLK = 1'b0;
	#40
	CLK = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("f:\\ise_test\\test_ddr_command.ano");

	// --------------------
	RESET_N = 1'b1;
	SADDR = 22'b0000000000000000000000; //0
	NOP = 1'b0;
	READA = 1'b0;
	WRITEA = 1'b0;
	REFRESH = 1'b0;
	PRECHARGE = 1'b0;
	LOAD_MODE = 1'b0;
	SC_CL = 2'b00; //0
	SC_RC = 2'b00; //0
	SC_RRD = 4'b0000; //0
	SC_PM = 1'b0;
	SC_BL = 4'b0000; //0
	REF_REQ = 1'b0;
	// --------------------
	#100 // Time=100 ns
	RESET_N = 1'b0;
	// --------------------
	#100 // Time=200 ns
	RESET_N = 1'b1;
	// --------------------
	#300 // Time=500 ns
	PRECHARGE = 1'b1;
	// --------------------
	#100 // Time=600 ns
	PRECHARGE = 1'b0;
	// --------------------
	#110 // Time=710 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_REF_ACK;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,REF_ACK,%b]",
			$time, REF_ACK);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_CM_ACK;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,CM_ACK,%b]",
			$time, CM_ACK);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_OE;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,OE,%b]",
			$time, OE);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SA;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SA,%b]",
			$time, SA);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_BA;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,BA,%b]",
			$time, BA);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_CS_N;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,CS_N,%b]",
			$time, CS_N);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_CKE;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,CKE,%b]",
			$time, CKE);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_RAS_N;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,RAS_N,%b]",
			$time, RAS_N);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_CAS_N;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,CAS_N,%b]",
			$time, CAS_N);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_WE_N;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,WE_N,%b]",
			$time, WE_N);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_do_nop;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,do_nop,%b]",
			$time, do_nop);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_do_reada;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,do_reada,%b]",
			$time, do_reada);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_do_writea;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,do_writea,%b]",
			$time, do_writea);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_do_refresh;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,do_refresh,%b]",
			$time, do_refresh);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_do_precharge;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,do_precharge,%b]",
			$time, do_precharge);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_do_load_mode;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,do_load_mode,%b]",
			$time, do_load_mode);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule