__projnav.log

xilinx的SPARTAN-3E入门开发板实例 根据官方公布的led移动范例改写。 原范例仅提供了源代码、烧写文件以及dos窗口下使用的烧写bat文件。 本实例采用了ise7.1i创建

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Started process "Compile HDL Simulation Libraries".

Process "Compile HDL Simulation Libraries" did not complete.



Project Navigator Auto-Make Log File
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Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling library compilation for SPARTAN-IIIE 
'\vsim.exe' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Source Tools ('AUTO_DETECT') => [null]

ERROR:CAEInterfaces:326 - COMPXLIB[env]: unable to find simulator (mti_se) executables

<ToolTip>: Specify the simulator executable path in the "Simulator Path"
           property under "Compile HDL Simulation Libraries" properties.

           IMPORTANT: Make sure that the license file/other environment
           variable for mti_se are properly set

Log file (compxlib.log) generated.

ERROR: compxlib failed
Process "Compile HDL Simulation Libraries" did not complete.


Project Navigator Auto-Make Log File
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Started process "HDL Converter".


ERROR: No input file specified for the "HDL Converter" process.
Please select an input file (ABEL or AHDL) from the property menu.
(Right click on the "HDL Converter" process name and select 'Properties')
Process "HDL Converter" did not complete due to error(s) reported by internal script.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/xillinx/mywork/ledleft/left_right_leds.vhd" in Library work.
Entity <left_right_leds> compiled.
Entity <left_right_leds> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <left_right_leds> (Architecture <Behavioral>).
INFO:Xst:1561 - "F:/xillinx/mywork/ledleft/left_right_leds.vhd" line 122: Mux is complete : default of case is discarded
Entity <left_right_leds> analyzed. Unit <left_right_leds> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <left_right_leds>.
    Related source file is "F:/xillinx/mywork/ledleft/left_right_leds.vhd".
    Found 8-bit register for signal <led>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006> created at line 110.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007> created at line 110.
    Found 1-bit register for signal <delay_rotary_q1>.
    Found 8-bit register for signal <led_drive>.
    Found 8-bit register for signal <led_pattern>.
    Found 1-bit register for signal <rotary_a_in>.
    Found 1-bit register for signal <rotary_b_in>.
    Found 1-bit register for signal <rotary_event>.
    Found 2-bit register for signal <rotary_in>.
    Found 1-bit register for signal <rotary_left>.
    Found 1-bit register for signal <rotary_press_in>.
    Found 1-bit register for signal <rotary_q1>.
    Found 1-bit register for signal <rotary_q2>.
    Summary:
	inferred  34 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <left_right_leds> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 12
 1-bit register                    : 8
 2-bit register                    : 1
 8-bit register                    : 3
# Multiplexers                     : 2
 1-bit 4-to-1 multiplexer          : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <left_right_leds> ...
Loading device for application Rf_Device from file '3s500e.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block left_right_leds, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                      20  out of   4656     0%  
 Number of Slice Flip Flops:            34  out of   9312     0%  
 Number of 4 input LUTs:                20  out of   9312     0%  
 Number of bonded IOBs:                 12  out of    232     5%  
 Number of GCLKs:                        1  out of     24     4%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 34    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.102ns (Maximum Frequency: 243.784MHz)
   Minimum input arrival time before clock: 2.447ns
   Maximum output required time after clock: 7.986ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\xillinx\mywork\ledleft/_ngo -nt
timestamp -uc left_right_leds.ucf -p xc3s500e-fg320-4 left_right_leds.ngc
left_right_leds.ngd 

Reading NGO file 'F:/xillinx/mywork/ledleft/left_right_leds.ngc' ...

Applying constraints in "left_right_leds.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "left_right_leds.ngd" ...

Writing NGDBUILD log file "left_right_leds.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s500efg320-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          23 out of   9,312    1%
  Number of 4 input LUTs:              20 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:                           14 out of   4,656    1%
    Number of Slices containing only related logic:      14 out of      14  100%
    Number of Slices containing unrelated logic:          0 out of      14    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          20 out of   9,312    1%
  Number of bonded IOBs:               12 out of     232    5%
    IOB Flip Flops:                    11
  Number of GCLKs:                     1 out of      24    4%

Total equivalent gate count for design:  395
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  121 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "left_right_leds_map.mrp" for details.




Started process "Place & Route".




Constraints file: left_right_leds.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment
C:/Xilinx.
   "left_right_leds" is an NCD, version 3.1, device xc3s500e, package fg320,
speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.13 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 24      4%
   Number of External IBUFs            4 out of 232     1%
      Number of LOCed IBUFs            4 out of 4     100%

   Number of External IOBs             8 out of 176     4%
      Number of LOCed IOBs             8 out of 8     100%

   Number of Slices                   14 out of 4656    1%
      Number of SLICEMs                0 out of 2328    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 6 secs 
Finished initial Timing Analysis.  REAL time: 6 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896eb) REAL time: 7 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 7 secs 

Phase 3.2
......
.................


Phase 3.2 (Checksum:98a243) REAL time: 11 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 11 secs 

Phase 5.8
.
.
Phase 5.8 (Checksum:990204) REAL time: 11 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 11 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 11 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs 

Writing design to file left_right_leds.ncd


Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 9 secs 

Starting Router

Phase 1: 95 unrouted;       REAL time: 14 secs 

Phase 2: 70 unrouted;       REAL time: 14 secs 

Phase 3: 10 unrouted;       REAL time: 14 secs 

Phase 4: 10 unrouted; (0)      REAL time: 14 secs 

Phase 5: 10 unrouted; (0)      REAL time: 14 secs 

Phase 6: 10 unrouted; (0)      REAL time: 14 secs 

Phase 7: 0 unrouted; (0)      REAL time: 14 secs 

Phase 8: 0 unrouted; (0)      REAL time: 14 secs 


Total REAL time to Router completion: 14 secs 
Total CPU time to Router completion: 12 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP | BUFGMUX_X1Y11| No   |   24 |  0.020     |  1.070      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "clk_BUFGP/IBUFG" PERIOD = 20 ns HIGH | 20.000ns   | 7.240ns    | 1    
   50%                                      |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 15 secs 
Total CPU time to PAR completion: 13 secs 

Peak Memory Usage:  122 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file left_right_leds.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s500e.nph' in environment
C:/Xilinx.
   "left_right_leds" is an NCD, version 3.1, device xc3s500e, package fg320,