left_right_leds.twr

来自「xilinx的SPARTAN-3E入门开发板实例 根据官方公布的led移动范例」· TWR 代码 · 共 65 行

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise f:\xillinx\mywork\ledleft\ledleft.ise -intstyle
ise -e 3 -l 3 -s 4 -xml left_right_leds left_right_leds.ncd -o
left_right_leds.twr left_right_leds.pcf


Design file:              left_right_leds.ncd
Physical constraint file: left_right_leds.pcf
Device,speed:             xc3s500e,-4 (ADVANCED 1.13 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: NET "clk_BUFGP/IBUFG" PERIOD = 20 ns HIGH 50%;

 70 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   7.240ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.240|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 70 paths, 0 nets, and 93 connections

Design statistics:
   Minimum period:   7.240ns (Maximum frequency: 138.122MHz)


Analysis completed Tue Dec 26 22:56:25 2006
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Peak Memory Usage: 108 MB