alu_tst_wave.ant

FPGA-CPLD_DesignTool,事例程序1-2

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG
// Verilog Annotation Test Bench created by
// HDL Bencher 5.1i
// Thu Dec 19 17:46:39 2002

`timescale 1ns/1ns

`define op_sub	1
`define op_and	2
`define op_or	3
`define op_unary	4
`define S1	0
`define S2	1
`define S3	2
`define S4	3
`define S5	4
`define S10	8
`define S20	9
`define S30	10
`define S40	11
`define S50	12
`define SX	7
`define op_add	0
`define start_code	2945842759

module testbench;
	reg clk;
	reg [7:0] a;
	reg [7:0] b;
	reg [2:0] opcode;
	wire [7:0] outp_a;
	wire [7:0] outp_s;

	alu UUT (
		.clk(clk),
		.a(a),
		.b(b),
		.opcode(opcode),
		.outp_a(outp_a),
		.outp_s(outp_s)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clk = 1'b0;
	#10
	clk = 1'b1;
	#10
	ANNOTATE_outp_a;
	ANNOTATE_outp_s;
	#40
	clk = 1'b0;
	#40
	clk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("j:\\temp\\exam\\hdlbencher-alu\\alu_vlog\\alu_tst_wave.ano");

	// --------------------
	a = 8'b00000000; //0
	b = 8'b11111111; //FF
	opcode = 3'b101; //5
	// --------------------
	#100 // Time=100 ns
	a = 8'b00000000; //0
	opcode = 3'b000; //0
	// --------------------
	#100 // Time=200 ns
	a = 8'b00000001; //1
	b = 8'b11111110; //FE
	opcode = 3'b101; //5
	// --------------------
	#100 // Time=300 ns
	a = 8'b00000010; //2
	opcode = 3'b100; //4
	// --------------------
	#100 // Time=400 ns
	a = 8'b00000011; //3
	b = 8'b11111101; //FD
	opcode = 3'b000; //0
	// --------------------
	#100 // Time=500 ns
	a = 8'b00000100; //4
	// --------------------
	#100 // Time=600 ns
	a = 8'b00000101; //5
	b = 8'b11111100; //FC
	opcode = 3'b110; //6
	// --------------------
	#100 // Time=700 ns
	a = 8'b00000110; //6
	opcode = 3'b011; //3
	// --------------------
	#100 // Time=800 ns
	a = 8'b00000111; //7
	b = 8'b11111011; //FB
	opcode = 3'b000; //0
	// --------------------
	#100 // Time=900 ns
	a = 8'b00001000; //8
	opcode = 3'b110; //6
	// --------------------
	#100 // Time=1000 ns
	a = 8'b00001001; //9
	b = 8'b11111010; //FA
	// --------------------
	#100 // Time=1100 ns
	a = 8'b00001010; //A
	opcode = 3'b000; //0
	// --------------------
	#100 // Time=1200 ns
	a = 8'b00001011; //B
	b = 8'b11111001; //F9
	opcode = 3'b110; //6
	// --------------------
	#100 // Time=1300 ns
	a = 8'b00001100; //C
	opcode = 3'b001; //1
	// --------------------
	#100 // Time=1400 ns
	a = 8'b00001101; //D
	b = 8'b11111000; //F8
	opcode = 3'b010; //2
	// --------------------
	#100 // Time=1500 ns
	a = 8'b00001110; //E
	opcode = 3'b001; //1
	// --------------------
	#100 // Time=1600 ns
	a = 8'b00001111; //F
	b = 8'b11110111; //F7
	// --------------------
	#100 // Time=1700 ns
	a = 8'b00010000; //10
	// --------------------
	#100 // Time=1800 ns
	a = 8'b00010001; //11
	b = 8'b11110110; //F6
	// --------------------
	#100 // Time=1900 ns
	a = 8'b00010010; //12
	// --------------------
	#100 // Time=2000 ns
	a = 8'b00010011; //13
	b = 8'b11110101; //F5
	// --------------------
	#200 // Time=2200 ns
	b = 8'b11110100; //F4
	// --------------------
	#10 // Time=2210 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("j:\\temp\\exam\\hdlbencher-alu\\alu_vlog\\alu_tst_wave.ano");

	// --------------------
	// --------------------
	#256 // Time=256 ns
	// --------------------
	#1954 // Time=2210 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_outp_a;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,outp_a,%b]",
			$time, outp_a);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_outp_s;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,outp_s,%b]",
			$time, outp_s);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule