代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5586176
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v1_0 is
generic(
c_decode_type : integer := 1;
c_enable_rlocs : integer := 0;
c_has_bports : integer :=
www.eeworm.com/read/159314/5586220
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v2_0 is
generic(
c_enable_rlocs : integer := 1;
c_encode_type : integer := 0;
c_force_code_disp: integer :
www.eeworm.com/read/159314/5586245
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v2_0 is
generic(
c_decode_type : integer := 1;
c_enable_rlocs : integer := 0;
c_has_bports : integer :=
www.eeworm.com/read/159314/5586374
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v1_0 is
generic(
c_enable_rlocs : integer := 1;
c_encode_type : integer := 0;
c_force_code_disp: integer :
www.eeworm.com/read/159314/5586383
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v3_0 is
generic(
c_decode_type : integer := 1;
c_enable_rlocs : integer := 0;
c_has_bports : integer :=
www.eeworm.com/read/154101/5641979
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pullup is
port(
o : out vl_logic
);
end pullup;
www.eeworm.com/read/154100/5642116
rsp xcoto_regencore_tenths.rsp
SETPROJECT c:\example-9-1\watch_sc
SET OverwriteFiles=true
SET SimulationOutputProducts = Verilog VHDL
SET XilinxFamily = Virtex2
EXECUTE tenths.xcp
www.eeworm.com/read/154098/5642247
out anal.out
Reading in the Synopsys verilog primitives.
J:/Example-8-1/Modular_Design/syn_modules/module_c/module_c.v:
www.eeworm.com/read/154098/5642267
sprj module_b.sprj
`timescale 1ns/1ns
`include "../module_b.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/154098/5642277
prj module_b.prj
`timescale 1ns/1ns
`include "../module_b.v"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"