_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v1_0 is
    generic(
        c_decode_type   : integer := 1;
        c_enable_rlocs  : integer := 0;
        c_has_bports    : integer := 0;
        c_has_ce        : integer := 0;
        c_has_ce_b      : integer := 0;
        c_has_code_err  : integer := 1;
        c_has_code_err_b: integer := 0;
        c_has_disp_err  : integer := 1;
        c_has_disp_err_b: integer := 0;
        c_has_disp_in   : integer := 0;
        c_has_disp_in_b : integer := 0;
        c_has_nd        : integer := 0;
        c_has_nd_b      : integer := 0;
        c_has_run_disp  : integer := 0;
        c_has_run_disp_b: integer := 0;
        c_has_sinit     : integer := 0;
        c_has_sinit_b   : integer := 0;
        c_has_sym_disp  : integer := 0;
        c_has_sym_disp_b: integer := 0;
        c_sinit_dout    : string  := "00000000";
        c_sinit_dout_b  : string  := "00000000";
        c_sinit_kout    : integer := 0;
        c_sinit_kout_b  : integer := 0;
        c_sinit_run_disp: integer := 0;
        c_sinit_run_disp_b: integer := 0
    );
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector(9 downto 0);
        dout            : out    vl_logic_vector(7 downto 0);
        kout            : out    vl_logic;
        ce              : in     vl_logic;
        ce_b            : in     vl_logic;
        clk_b           : in     vl_logic;
        din_b           : in     vl_logic_vector(9 downto 0);
        disp_in         : in     vl_logic;
        disp_in_b       : in     vl_logic;
        sinit           : in     vl_logic;
        sinit_b         : in     vl_logic;
        code_err        : out    vl_logic;
        code_err_b      : out    vl_logic;
        disp_err        : out    vl_logic;
        disp_err_b      : out    vl_logic;
        dout_b          : out    vl_logic_vector(7 downto 0);
        kout_b          : out    vl_logic;
        nd              : out    vl_logic;
        nd_b            : out    vl_logic;
        run_disp        : out    vl_logic;
        run_disp_b      : out    vl_logic;
        sym_disp        : out    vl_logic_vector(1 downto 0);
        sym_disp_b      : out    vl_logic_vector(1 downto 0)
    );
end decode_8b10b_v1_0;