_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v1_0 is
    generic(
        c_enable_rlocs  : integer := 1;
        c_encode_type   : integer := 0;
        c_force_code_disp: integer := 0;
        c_force_code_disp_b: integer := 0;
        c_force_code_val: string  := "0101010101";
        c_force_code_val_b: string  := "0101010101";
        c_has_bports    : integer := 0;
        c_has_ce        : integer := 1;
        c_has_ce_b      : integer := 0;
        c_has_disp_in   : integer := 1;
        c_has_disp_in_b : integer := 0;
        c_has_disp_out  : integer := 1;
        c_has_disp_out_b: integer := 0;
        c_has_force_code: integer := 1;
        c_has_force_code_b: integer := 0;
        c_has_kerr      : integer := 1;
        c_has_kerr_b    : integer := 0;
        c_has_nd        : integer := 1;
        c_has_nd_b      : integer := 0
    );
    port(
        din             : in     vl_logic_vector(7 downto 0);
        kin             : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        force_code      : in     vl_logic;
        force_disp      : in     vl_logic;
        disp_in         : in     vl_logic;
        dout            : out    vl_logic_vector(9 downto 0);
        disp_out        : out    vl_logic;
        kerr            : out    vl_logic;
        nd              : out    vl_logic;
        din_b           : in     vl_logic_vector(7 downto 0);
        kin_b           : in     vl_logic;
        clk_b           : in     vl_logic;
        ce_b            : in     vl_logic;
        force_code_b    : in     vl_logic;
        force_disp_b    : in     vl_logic;
        disp_in_b       : in     vl_logic;
        dout_b          : out    vl_logic_vector(9 downto 0);
        disp_out_b      : out    vl_logic;
        kerr_b          : out    vl_logic;
        nd_b            : out    vl_logic
    );
end encode_8b10b_v1_0;