代码搜索:testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/183931/9130109
v test.v
`timescale 10ns/100ps
module testBench;
reg clock,d,reset;
dff d1(q,clock,d,reset); // module substantiation
always // clock
#10 clock=~clock;
initial begin // test procedur
www.eeworm.com/read/364280/9915117
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity testbench is
end testbench;
www.eeworm.com/read/364280/9915162
mti multl6s.cr.mti
G:/Q71/verilog/multl6s/mult16S_tb.tf {1 {vlog -work work -novopt -y D:/Modeltech_6.2b/examples G:/Q71/verilog/multl6s/mult16S_tb.tf
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
www.eeworm.com/read/364280/9915173
tf mult16s_tb.tf
module testbench();
// Inputs
reg [15:0] A;
reg [15:0] B;
// Outputs
wire [31:0] P;
// Instantiate the UUT
mult16S uut (.P(P), .A(A), .B(B));
initial
$moni
www.eeworm.com/read/361898/10029722
vhd a8259tb.vhd
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : a8259tb.vhd
-- USED IN : a8259top.vhd (A8259 and test
www.eeworm.com/read/281220/10255924
do test_post.do
-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved
vlib work
vmap work work
vcom -reportprogress 300 -work work StrataFlash3V.vhd
vcom -reportprogress 300 -work work timesim.vhd
vcom -re
www.eeworm.com/read/355262/10283465
txt 关于modelsim的使用.txt
由于modelsim命令模式查看波形不方便,所以我们在仿真结束后查看波形进行查看,就需要存储波形。下面是网上的一点东西,给我的仿真带来了方便。
VCD system task calls in the Verilgsource code.
.可以通过在源代码中添加语句来实现
initial begin
$Dumpfile("./test.fsdb");
$Dumpvars(0,test)
www.eeworm.com/read/355262/10283487
txt 我的仿真工作流程.txt
这是献给大家的第二篇,文章详细说明了本人近一年来,自己摸索出来的一套仿真工作流程。接触过Modelsim这类软件的朋友可能都会感觉上手比较困难,原因有二:一、对仿真机制不了解,对基于source+<mark>testbench</mark>的工作流程不熟悉(大多数朋友接触FPGA仿真可能以waveform的方式);二、对软件的安装和使用不熟悉,Modelsim软件破解和平时常用软件相比要麻烦一些,也不像常用软件那样易于上手 ...
www.eeworm.com/read/425249/10367201
do run.do
vlib ../simulation/postsynth
vmap postsynth ../simulation/postsynth
vcom -93 -explicit -work postsynth {C:/Actelprj/connect20090223/synthesis/connect.vhd}
vcom -93 -explicit -work postsynth {C:/Act
www.eeworm.com/read/348755/10868723
do wave_color.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -color Red -format Logic /testbench/reset
add wave -noupdate -color Orange -format Logic /testbench/clk
add wave -noupdate -co