run.do

fpga从FIFO读数据并上传到双口ram中。

vlib ../simulation/postsynth
vmap postsynth ../simulation/postsynth
vcom -93 -explicit -work postsynth {C:/Actelprj/connect20090223/synthesis/connect.vhd}
vcom -93 -explicit -work postsynth {C:/Actelprj/connect20090223/stimulus/testbench.vhd}
vsim -t 1ps postsynth.testbench
add wave /testbench/*
run 1000ns