test_post.do

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved

vlib work
vmap work work
vcom -reportprogress 300 -work work StrataFlash3V.vhd
vcom -reportprogress 300 -work work timesim.vhd
vcom -reportprogress 300 -work work testbench.vhd
vsim work.testbench
view wave
do wave_post.do
view structure
view signals
vcd file cf_plus.vcd
vcd add testbench/*

run 4 ms