mult16s_tb.tf

来自「Verilog 经典实例」· TF 代码 · 共 38 行

module testbench();

// Inputs
    reg [15:0] A;
    reg [15:0] B;


// Outputs
    wire [31:0] P;


// Instantiate the UUT
    mult16S uut (.P(P), .A(A), .B(B));

initial
    $monitor($time, " A = %d  B = %d   P=", A, B, P);

initial begin
   #100 begin A = 25; B=25; end
   #100 begin A = 1; B=200; end
   #100 begin A = 250; B=1; end
   #100 begin A = 0; B=100; end
   #100 begin A = 125; B=0; end
   #100 begin A = 235; B=428; end
   #100 begin A = 255; B=177; end

end

//Finish the simulation at time 800
initial begin
    #800 $finish;
end

endmodule