代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/152701/12092261
v addertestbench.v
//testbench for 16-bit adder*/
//---------------------------------
`timescale 1ns/1ns
`include "adder0215.v"
`define clk_cycle 50
module addertest;
parameter Numbits=16;
reg [Numbits-1:0
www.eeworm.com/read/152701/12092269
bak addertestbench.v.bak
//testbench for 16-bit adder*/
//---------------------------------
`timescale 1ns/1ns
`include "adder0215.v"
`define clk_cycle 50
module addertest;
parameter Numbits=16;
reg [Numbits-1:0
www.eeworm.com/read/151305/12220312
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/149028/12408074
vhd 63_stim.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
www.eeworm.com/read/131754/14131467
vhd micro_master_tb.vhd
-- micro_master_tb.vhd
--
-- Created: 6/17/99 ALS
-- This file emulates the uC that interfaces to the I2C design. This testbench
-- will interface to one I2C post-layout design and configure this
www.eeworm.com/read/118540/14864311
vhd mouse_tb.vhd
-- VHDL Test Bench Created from source file mouse.vhd -- 10:55:02 07/01/2002
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for th
www.eeworm.com/read/219674/14870941
vhd freq_change_test.vhd
-- VHDL Test Bench Created from source file freq_change.vhd -- 18:48:27 12/13/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector
www.eeworm.com/read/219674/14871027
vhd control_unite_test.vhd
-- VHDL Test Bench Created from source file control_unite.vhd -- 22:18:34 12/13/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vecto
www.eeworm.com/read/219674/14871085
vhd free_change_test.vhd
-- VHDL Test Bench Created from source file free_change.vhd -- 12:54:06 12/18/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector
www.eeworm.com/read/210233/15203379
vhw qd_tw.vhw
-- E:\VHDL\WAITPAST\QIANGDAQI4REN
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Mar 24 14:51:18 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- you