control_unite_test.vhd

本代码介绍了使用VHDL开发FPGA的一般流程

-- VHDL Test Bench Created from source file control_unite.vhd -- 22:18:34 12/13/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY control_unite_control_unite_test_vhd_tb IS
END control_unite_control_unite_test_vhd_tb;

ARCHITECTURE behavior OF control_unite_control_unite_test_vhd_tb IS 

	COMPONENT control_unite
	PORT(
		Switch : IN std_logic_vector(0 to 2);
		clk1 : IN std_logic;
		clk10 : IN std_logic;
		clk100 : IN std_logic;
		RST : IN std_logic;          
		gate : OUT std_logic;
		CLEAR : OUT std_logic;
		LOAD : OUT std_logic;
		LED_point : OUT std_logic_vector(0 to 2)
		);
	END COMPONENT;

	SIGNAL Switch :  std_logic_vector(0 to 2);
	SIGNAL clk1 :  std_logic;
	SIGNAL clk10 :  std_logic;
	SIGNAL clk100 :  std_logic;
	SIGNAL RST :  std_logic;
	SIGNAL gate :  std_logic;
	SIGNAL CLEAR :  std_logic;
	SIGNAL LOAD :  std_logic;
	SIGNAL LED_point :  std_logic_vector(0 to 2);

BEGIN

	uut: control_unite PORT MAP(
		Switch => Switch,
		clk1 => clk1,
		clk10 => clk10,
		clk100 => clk100,
		RST => RST,
		gate => gate,
		CLEAR => CLEAR,
		LOAD => LOAD,
		LED_point => LED_point
	);


-- *** Test Bench - User Defined Section ***
   tb1 : PROCESS
   BEGIN
      clk100<='0';
	 wait for 10 ns;
	 clk100<='1';
	 wait for 10 ns;
   END PROCESS;

   tb2 : PROCESS
   BEGIN
      clk10<='0';
	 wait for 100 ns;
	 clk10<='1';
	 wait for 100 ns;
   END PROCESS;


   tb3 : PROCESS
   BEGIN
      clk1<='0';
	 wait for 200 ns;
	 clk1<='1';
	 wait for 200 ns;
   END PROCESS;

   tb4 : PROCESS
   BEGIN
   	 Switch<="011";
	 wait for 3 sec;
	 Switch<="101";
	 wait for 3 sec;
	 Switch<="110";
	 wait for 3 sec;
   END PROCESS;

     tb5 : PROCESS
   BEGIN
	 RST<='1';
	 wait for 500 ns;
	 RST<='0';
	 wait for 10 ns;
	 RST<='1';
	 wait for 600 ns;
   END PROCESS;

-- *** End Test Bench - User Defined Section ***

END;