freq_change_test.vhd

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 58 行

-- VHDL Test Bench Created from source file freq_change.vhd -- 18:48:27 12/13/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY freq_change_freq_change_test_vhd_tb IS
END freq_change_freq_change_test_vhd_tb;

ARCHITECTURE behavior OF freq_change_freq_change_test_vhd_tb IS 

	COMPONENT freq_change
	PORT(
		clk_in : IN std_logic;          
		clk_out1 : OUT std_logic;
		clk_out10 : OUT std_logic;
		clk_out100 : OUT std_logic;
		CP10k : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clk_in :  std_logic;
	SIGNAL clk_out1 :  std_logic;
	SIGNAL clk_out10 :  std_logic;
	SIGNAL clk_out100 :  std_logic;
	SIGNAL CP10k :  std_logic;

BEGIN

	uut: freq_change PORT MAP(
		clk_in => clk_in,
		clk_out1 => clk_out1,
		clk_out10 => clk_out10,
		clk_out100 => clk_out100,
		CP10k => CP10k
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      clk_in<='0';
      wait for 15.625 ns;
	 clk_in<='1';
      wait for 15.625 ns;
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;