addertestbench.v

16位高速加法器

//testbench for 16-bit adder*/
//---------------------------------

`timescale  1ns/1ns
`include "adder0215.v"
`define clk_cycle 50

module addertest;
	parameter Numbits=16;
	reg [Numbits-1:0]  a,b,sum_comp;         //sumcomp为仿真结果的比较值
	reg cin,cout_comp;
	wire [Numbits-1:0] sum;
	wire cout; 	
	reg  [15:0] mem[0:54];
	integer  i,flag;                        //flag为验证不符合标志，flag=1时验证不符合  
	
	adder_16  simu(.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));   	       
	
	initial
	   begin	   
	      $readmemh("testfile",mem);
	      
	      for(i=0;i<54;i=i+5)
	      	begin
	      	   a=mem[i];
	      	   b=mem[i+1];
	      	   cin=mem[i+2][0];
	      	   sum_comp=mem[i+3];
	      	   cout_comp=mem[i+4][0];
	      	   #100;	      	   
	      	   $display("a= %b b= %b cin= %b sum= %b cout= %b",a,b,cin,sum,cout);
	      	   if((sum!==sum_comp)||(cout!==cout_comp))
	      	   	begin
	      	   	   $display("adder_16 simulation  mismatch on  testvector  %h, %h, %h",mem[i],mem[i+1],mem[i+2][0]);
	      	   	   flag=1;
	      	   	end	      	   
	        end
	        
	     if(flag!=1)
	     	  $display("adder_16 simulate  successfully.");	        		                      	
	   end		 	
endmodule