63_stim.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Author    : yzf
-- Created On: Fri Dec  8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp

--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change all the number based on binary into the decimal number.
--				because our compiler now can't handle binary based number.
use WORK.types.all;

architecture BENCH of test_gcd_disp is 
	component gcd_disp
	    PORT(
		RESET: IN BIT;
		CLK: IN BIT;
		RST: IN BIT;
		XIN: IN NAT8;
		YIN: IN NAT8;
		RDY: OUT BIT;
		OUTP: OUT NAT8;
		UNIT1: OUT BIT_VECTOR ( 6 downto 0 );
		UNIT2: OUT BIT_VECTOR ( 6 downto 0 )
	    );
	end component;
	signal t_RESET:BIT;
	signal t_CLK:BIT;
	signal t_RST:BIT;
	signal t_XIN:NAT8;
	signal t_YIN:NAT8;
	signal t_RDY:BIT := '0';
	signal t_OUTP:NAT8;
	signal t_UNIT1:BIT_VECTOR ( 6 downto 0 );
	signal t_UNIT2:BIT_VECTOR ( 6 downto 0 );


for all : gcd_disp use entity work.gcd_disp;
begin
	gcd_disp_I1: gcd_disp 
	    port map (
		RESET => t_RESET,
		CLK => t_CLK,
		RST => t_RST,
		XIN => t_XIN,
		YIN => t_YIN,
		RDY => t_RDY,
		OUTP => t_OUTP,
		UNIT1 => t_UNIT1,
		UNIT2 => t_UNIT2
	    );

	gcd_disp_driver: process
	begin
     t_Reset <= '0';
--  The following 2 lines are modified by : Wu Qing-ping. Apr 24,1998
--  Reason:	Our compiler cannot handle the binary display method
--     t_XIN <= 2#00000001# ;
--     t_YIN <= 2#00000000# ;
	 t_XIN <= 240;
	 t_YIN <= 90;

	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 t_rst <= '0';
     wait until t_RDY = '1';
     --assert t_outp = 2#00000001#
     assert t_outp =30 
       report "t_oup does not match in pattern 1"
         severity error;
   
   
   -- t_XIN and t_YIN are small and divisible x = 2, y = 1, reset = 0
   
 --    t_XIN <= 2#00000010# ;
 --    t_YIN <= 2#00000001# ;
     t_XIN <= 220;
     t_YIN <= 121;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; 
	 t_rst <= '0';
     wait until t_RDY = '1';
   
  --   assert t_outp = 2#00000001#
     assert t_outp = 11
      report "t_oup does not match in pattern 2"
         severity error;
   
   -- t_XIN and t_YIN are small and divisible 2 times x = 6, y = 3, reset = 0
   
  --   t_XIN <= 2#00000110# ;
 --    t_YIN <= 2#00000011# ;
    t_XIN <= 6;
     t_YIN <= 3 ;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; 
	 t_rst <= '0';
     wait until t_RDY = '1';
   
--     assert t_outp = 2#00000011#
     assert t_outp = 3
       report "t_oup does not match in pattern 3"
         severity error;
   
   -- t_XIN and t_YIN are small and divisible 4 times x = 12, y = 3, reset = 0
   
--     t_XIN <= 2#00001100# ;
 --    t_YIN <= 2#00000011# ;
     t_XIN <= 6;
     t_YIN <= 3;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; 
	 t_rst <= '0';
     wait until t_RDY = '1';
--     assert t_outp = 2#00000011#
     assert t_outp = 3 
       report "t_oup does not match in pattern 4"
         severity error;
   
     
   
   -- t_XIN and t_YIN are small and divisible x = 1, y = 2, reset = 0
   
 --    t_XIN <= 2#00000001# ;
 --    t_YIN <= 2#00000010# ;
     t_XIN <= 1;
     t_YIN <= 2;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 t_rst <= '0';
     wait until t_RDY = '1';
   
  --   assert t_outp = 2#00000001#
     assert t_outp = 1
       report "t_oup does not match in pattern 5"
         severity error;
   
   -- t_XIN and t_YIN are small and divisible 2 times x = 3, y = 6, reset = 0
   
--     t_XIN <= 2#00000011# ;
 --    t_YIN <= 2#00000110# ;
     t_XIN <= 3 ;
     t_YIN <= 6 ;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 t_rst <= '0';
     wait until t_RDY = '1';
 --   assert t_outp = 2#00000011#
    assert t_outp = 3
      report "t_oup does not match in pattern 6"
         severity error;
   
   -- t_XIN and t_YIN are small and divisible 4 times x = 3, y = 12, reset = 0
   
--     t_XIN <= 2#00000011# ;
--     t_YIN <= 2#00001100# ;
     t_XIN <= 3;
     t_YIN <= 12;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 t_rst <= '0';
     wait until t_RDY = '1';
--     assert t_outp = 2#00000011#
     assert t_outp = 3

       report "t_oup does not match in pattern 7"
         severity error;
   
   -- t_XIN and t_YIN are small and divisible 4 times x = 12, y = 6, reset = 1
   
 --    t_XIN <= 2#00001100# ;
 --    t_YIN <= 2#00000110# ;
     t_XIN <= 12 ;
     t_YIN <= 6 ;
	 t_rst <= '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 wait until t_CLK = '1'; wait until t_CLK = '1';
	 t_rst <= '0';
     wait until t_RDY = '1';
--     assert t_outp = 2#00000110#
     assert t_outp =6 
       report "t_oup does not match in pattern 8"
         severity error;
   
   
	 assert false
	 report "---End of Simulation---"
	 severity error;

	end process;
    gcd_clk:process
    begin
	 while (t_Reset = '0') loop
	  t_clk <= '0';
	  wait for 50 ns;

	  t_clk <= '1';
	  wait for 50 ns;

     end loop;
	end process;
end BENCH;