代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/292720/3942202
do ddr2_eval.do
if {![file exists work]} {
vlib work
}
vmap work work
#==== compile
vlog +libext+.v -y ../../../models/mem \
+incdir+../../../testbench/tests/ecp2m \
+incdir+../../src/params \
+incdir+
www.eeworm.com/read/292720/3942203
do ddr2_eval_timing.do
if {![file exists work]} {
vlib work
}
vmap work work
#==== compile
vlog +libext+.v -y ../../../models/mem \
+incdir+../../../testbench/tests/ecp2m \
+incdir+../../src/params \
+incdir+
www.eeworm.com/read/434670/1868869
vhd micro_tb.vhd
-- micro_tb.vhd
--
-- Created: 6/3/99 ALS
-- This file emulates the uC that interfaces to the I2C design. This testbench
-- will interface to two instantiations of the I2C design, one will be conf
www.eeworm.com/read/379942/2666210
readme_71t67802
IDT71V2578 - s133/150/166/183/200 verilog models/testbench
----------------------------------------------------------
07/09/99
rev01 - devoloped from IDT71V2576_rev01
-------------------------
www.eeworm.com/read/263610/4301475
readme_71t67802
IDT71V2578 - s133/150/166/183/200 verilog models/testbench
----------------------------------------------------------
07/09/99
rev01 - devoloped from IDT71V2576_rev01
------------------------------
www.eeworm.com/read/286093/8788620
vhd qdqaaa.vhd
-- VHDL Test Bench Created from source file qdq.vhd -- 18:28:38 06/20/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/286093/8788908
vhd bjqaaa.vhd
-- VHDL Test Bench Created from source file bjq.vhd -- 12:34:03 05/30/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/286093/8788925
vhd qdq.vhd
-- VHDL Test Bench Created from source file qdq.vhd -- 09:08:23 06/13/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/286093/8788930
vhd dsqaaa.vhd
-- VHDL Test Bench Created from source file dsq.vhd -- 12:30:00 05/16/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/286093/8788931
vhd ymqaaa.vhd
-- VHDL Test Bench Created from source file ymq.vhd -- 12:32:40 05/30/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the