qdqaaa.vhd

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-- VHDL Test Bench Created from source file qdq.vhd -- 18:28:38 06/20/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY qdq_qdqaaa_vhd_tb IS
END qdq_qdqaaa_vhd_tb;

ARCHITECTURE behavior OF qdq_qdqaaa_vhd_tb IS 

	COMPONENT qdq
	PORT(
		en : IN std_logic;
		clk : IN std_logic;
		q2 : IN std_logic;
		qiang : IN std_logic_vector(7 downto 0);          
		qz : OUT std_logic_vector(3 downto 0);
		q1 : OUT std_logic
		);
	END COMPONENT;

	SIGNAL en :  std_logic;
	SIGNAL clk :  std_logic;
	SIGNAL q2 :  std_logic;
	SIGNAL qiang :  std_logic_vector(7 downto 0);
	SIGNAL qz :  std_logic_vector(3 downto 0);
	SIGNAL q1 :  std_logic;

BEGIN

	uut: qdq PORT MAP(
		en => en,
		clk => clk,
		q2 => q2,
		qiang => qiang,
		qz => qz,
		q1 => q1
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      en<='0';wait for 10 ms;en<='1';	wait;
   END PROCESS;
   ta: process
   begin
   q2<='0';wait;
    end process;
    tc:process
    begin
      clk<='0';wait for 0.5 ms;
	 clk<='1';wait for 0.5 ms;
	 end process;
    td:process
    begin
      wait for 20 ms;qiang<="00010000";wait for 10 ms;qiang<="01000000";wait;
	 end process;
-- *** End Test Bench - User Defined Section ***

END;