qdq.vhd

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-- VHDL Test Bench Created from source file qdq.vhd -- 09:08:23 06/13/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY qdq_QDQ_vhd_tb IS
END qdq_QDQ_vhd_tb;

ARCHITECTURE behavior OF qdq_QDQ_vhd_tb IS 

	COMPONENT qdq
	PORT(
		en1 : IN std_logic;
		en : IN std_logic;
		clkin : IN std_logic;
		qqd : IN std_logic_vector(7 downto 0);          
		states : OUT std_logic_vector(3 downto 0);
		q1 : OUT std_logic
		);
	END COMPONENT;

	SIGNAL en1 :  std_logic;
	SIGNAL en :  std_logic;
	SIGNAL clkin :  std_logic;
	SIGNAL qqd :  std_logic_vector(7 downto 0);
	SIGNAL states :  std_logic_vector(3 downto 0);
	SIGNAL q1 :  std_logic;

BEGIN

	uut: qdq PORT MAP(
		en1 => en1,
		en => en,
		clkin => clkin,
		qqd => qqd,
		states => states,
		q1 => q1
	);


-- *** Test Bench - User Defined Section ***
   ta : PROCESS
   BEGIN
	 clkin<='0';wait for 15.625 ns;
	 clkin<='1';wait for 15.625 ns;
   END PROCESS;
   tb : PROCESS
   BEGIN
      wait for 50 ms;
	 qqd<="00010000";wait for 10 ms; qqd<="01000000";
	 END PROCESS; 
    td : PROCESS
    BEGIN
       en1<='0'; wait for 10 ms;
	  en1<='1';
	  en<='0';wait;
	END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;