dsqaaa.vhd

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-- VHDL Test Bench Created from source file dsq.vhd -- 12:30:00 05/16/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY dsq_dsqaaa_vhd_tb IS
END dsq_dsqaaa_vhd_tb;

ARCHITECTURE behavior OF dsq_dsqaaa_vhd_tb IS 

	COMPONENT dsq
	PORT(
		en1 : IN std_logic;
		hold : IN std_logic;
		clkin1 : IN std_logic;          
		q2 : OUT std_logic;
		data1 : OUT std_logic_vector(3 downto 0);
		data2 : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL en1 :  std_logic;
	SIGNAL hold :  std_logic;
	SIGNAL clkin1 :  std_logic;
	SIGNAL q2 :  std_logic;
	SIGNAL data1 :  std_logic_vector(3 downto 0);
	SIGNAL data2 :  std_logic_vector(3 downto 0);

BEGIN

	uut: dsq PORT MAP(
		en1 => en1,
		hold => hold,
		clkin1 => clkin1,
		q2 => q2,
		data1 => data1,
		data2 => data2
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
	 clkin1<='0';wait for 0.5 ms;
	 clkin1<='1';wait for 0.5 ms;
   END PROCESS;

   ta : PROCESS
   BEGIN
     en1<='0'; wait for 500 ms;
     en1<='1';wait for 12000 ms;
     

	 END PROCESS;

	td: PROCESS
	 BEGIN
	   
	   hold<='0';wait for 16000 ms;
	   hold<='1';wait for 6000 ms;
	   
	 END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;