bjqaaa.vhd

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-- VHDL Test Bench Created from source file bjq.vhd -- 12:34:03 05/30/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY bjq_bjqaaa_vhd_tb IS
END bjq_bjqaaa_vhd_tb;

ARCHITECTURE behavior OF bjq_bjqaaa_vhd_tb IS 

	COMPONENT bjq
	PORT(
		b1 : IN std_logic;
		b2 : IN std_logic;
		b3 : IN std_logic;
		clkin1 : IN std_logic;          
		bout : OUT std_logic
		);
	END COMPONENT;

	SIGNAL b1 :  std_logic;
	SIGNAL b2 :  std_logic;
	SIGNAL b3 :  std_logic;
	SIGNAL clkin1 :  std_logic;
	SIGNAL bout :  std_logic;

BEGIN

	uut: bjq PORT MAP(
		b1 => b1,
		b2 => b2,
		b3 => b3,
		clkin1 => clkin1,
		bout => bout
	);


-- *** Test Bench - User Defined Section ***
  ta: PROCESS
    BEGIN
      clkin1<='1';wait for 0.5 ms;
	 clkin1<='0';wait for 0.5 ms;
	 END PROCESS;
    tb : PROCESS  
   BEGIN
       b1<='0'; wait for 10 ms;
        b1<='1';wait;
   END PROCESS;
   tc : PROCESS
    BEGIN
       b2<='0';wait for 200 ms;
	  b2<='1'; wait;
	  END PROCESS;
	td: PROCESS
	BEGIN
	  b3<='0';wait for 400 ms;
       b3<='1';wait;
	  END PROCESS;
	 


-- *** End Test Bench - User Defined Section ***

END;