ymqaaa.vhd

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-- VHDL Test Bench Created from source file ymq.vhd -- 12:32:40 05/30/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ymq_ymqaaa_vhd_tb IS
END ymq_ymqaaa_vhd_tb;

ARCHITECTURE behavior OF ymq_ymqaaa_vhd_tb IS 

	COMPONENT ymq
	PORT(
		int : IN std_logic_vector(3 downto 0);          
		out7 : OUT std_logic_vector(6 downto 0)
		);
	END COMPONENT;

	SIGNAL int :  std_logic_vector(3 downto 0);
	SIGNAL out7 :  std_logic_vector(6 downto 0);

BEGIN

	uut: ymq PORT MAP(
		int => int,
		out7 => out7
	);


-- *** Test Bench - User Defined Section ***
  tb : PROCESS
   BEGIN
      wait for 10 ms;
	 int<="1000";wait for 50 ms;
	 int<="0100";wait for 20 ms;
	 int<="1010";
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;