代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/137358/13326720
vhd alarmreg.vhd
library ieee; --闹钟寄存器
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alarmreg is
port(clk:in std_logic;
alarmload:in std_logic;
www.eeworm.com/read/323655/13330728
vhd cnt8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT8 IS
PORT (
CLK, LD : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CAO
www.eeworm.com/read/323586/13334704
vhd clock.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( clk : in std_logic; --1Hz
reset : in std_logic; --复位信号
www.eeworm.com/read/137265/13336552
vhd sdr_sdram.vhd
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Alte
www.eeworm.com/read/323126/13349541
vhd reg16b.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity reg16b is
port( load:in std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15
www.eeworm.com/read/322263/13383860
vhd display.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity display is
port(
clk: in std_logic;
data: in std_
www.eeworm.com/read/321949/13392339
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/321949/13392367
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/321164/13411432
txt baweierjinzhibijiaoqi.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comp_8 is
port(a,b:in std_logic_vector(7 downto 0);
y:out std_logic_vector(1 downto 0));
end comp_8;
arch
www.eeworm.com/read/321164/13411434
txt suocunqi.txt
library ieee;
use ieee.std_logic_1164.all;
entity suocunqi is
port(clr,clk,ena,oe:in std_logic;
d:in std_logic_vector(7 downto 0);
q:buffer std_logic_vector(7