alarmreg.vhd

来自「具有多种功能的电子钟：闹钟」· VHDL 代码 · 共 22 行

library ieee;  --闹钟寄存器
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alarmreg is
 port(clk:in std_logic;
	  alarmload:in std_logic;                       --闹钟信号
	  buffertime:in std_logic_vector(23 downto 0);  --时间数据
 	  alarmtime: out std_logic_vector(23 downto 0));--寄存器输出
end alarmreg;
architecture ala of alarmreg is
begin
 process(clk)
begin
 if rising_edge(clk)then
   if(alarmload='1')then
    alarmtime<=buffertime;
end if;
end if;
end process;
end ala;