statemachine.vhd

来自「具有多种功能的电子钟：闹钟」· VHDL 代码 · 共 69 行

library ieee;  --报时和闹钟开关状态机
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity statemachine is
	port(clk: in std_logic;
		 keyc,keyd: in std_logic;  --c报时开关；d闹钟开关；
         alarmon: out std_logic;    --闹钟信号 
		 houralarmon :out std_logic);  --计数时间信号
end statemachine ;
architecture sta of statemachine is
	type state is (s_off,s_on);
--闹钟开关状态
signal palarm :state:=s_off;
signal nalarm :state:=s_off;
--报时开关状态
signal phour :state:=s_off;
signal nhour :state:=s_off;

signal q:integer:=0;
begin
 process(clk)
begin
	if(clk'event and clk='1')then
     palarm<=nalarm;
     phour<=nhour;
end if;
end process;


process(palarm,keyd)
begin
 if(palarm=s_on)then
	if(keyd='1')then
	  nalarm<=s_off;
else
	  nalarm<=palarm;
 end if;
  alarmon<='1';
else
	if(keyd='1')then
	  nalarm<=s_on;
else
	  nalarm<=palarm;
 end if;
  alarmon<='0';
end if;
end process;

process(phour,keyc)
begin
 if(phour=s_on)then
	if(keyc='1')then
	  nhour<=s_off;
else
	  nhour<=phour;
 end if;
  houralarmon<='1';
else
	if(keyc='1')then
	  nhour<=s_on;
else
	  nhour<=phour;
 end if;
  houralarmon<='0';
end if;
end process;
end sta;