clock.vhd

这个是数字电子时钟

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( clk : in std_logic; --1Hz
      reset : in std_logic; --复位信号
      dins : in std_logic_vector(6 downto 0);--秒钟预置
      dinm : in std_logic_vector(6 downto 0);--分钟预置
      dinh : in std_logic_vector(5 downto 0);--时钟预置
      secondl: out std_logic_vector(6 downto 0);--秒钟低位输出
      secondh: out std_logic_vector(6 downto 0); --秒钟高位输出
      minutel: out std_logic_vector(6 downto 0); --分钟低位输出
      minuteh: out std_logic_vector(6 downto 0); --分钟高位输出
      hourl: out std_logic_vector(6 downto 0); --小时低位输出
      hourh: out std_logic_vector(6 downto 0)); --小时高位输出
      end clock;
      architecture Behavioral of clock is
      component counter10 is
      Port ( clk : in std_logic;
      reset : in std_logic;
      din : in std_logic_vector(3 downto 0);
      dout : out std_logic_vector(3 downto 0);
      c:out std_logic);
      end component;

      component counter6 is
      Port ( clk : in std_logic;
      reset : in std_logic;
      din : in std_logic_vector(2 downto 0);
      dout : out std_logic_vector(2 downto 0);
      c:out std_logic);
      end component;

      component counter24 is
      Port ( clk : in std_logic;
      reset : in std_logic;
      din : in std_logic_vector(5 downto 0);
      dout : out std_logic_vector(5 downto 0));
      end component;

      component decoder is
      Port (din:in std_logic_vector(3 downto 0 ); 
      dout:out std_logic_vector(6 downto 0)); 
      end component;

      signal c1,c2,c3,c4:std_logic;
      signal doutsl,doutml:std_logic_vector(3 downto 0);
      signal doutsh,doutmh:std_logic_vector(2 downto 0);
      signal douth:std_logic_vector(5 downto 0);
      signal rdoutsh,rdoutmh:std_logic_vector(3 downto 0); 
      signal rdouth:std_logic_vector(7 downto 0);
      begin
      rdoutsh <= '0'&doutsh; --将秒钟高位数据变为4位，再进行译码
      rdoutmh <= '0'&doutmh; --将分钟高位数据变为4位，再进行译码
      rdouth <="00"&douth; --将时钟高位数据变为4位，再进行译码
      u0: counter10 port map( clk=>clk,reset=>reset,din=>dins(3 downto 0),dout=>doutsl,c=>c1);
      u1: counter6 port map( clk=>c1,reset=>reset,din=>dins(6 downto 4),dout=>doutsh,c=>c2);
      u2: counter10 port map( clk=>c2,reset=>reset,din=>dinm(3 downto 0),dout=>doutml,c=>c3);
      u3: counter6 port map( clk=>c3,reset=>reset,din=>dinm(6 downto 4),dout=>doutmh,c=>c4);
      u4: counter24 port map( clk=>c4,reset=>reset,din=>dinh,dout=>douth);
      u5: decoder port map( din => doutsl,dout => secondl); --秒的低位
      u6: decoder port map( din => rdoutsh,dout => secondh); --秒的高位
      u7: decoder port map( din => doutml,dout => minutel); --分的低位 
      u8: decoder port map( din => rdoutmh,dout => minuteh); --分的高位
      u9: decoder port map( din => rdouth(3 downto 0),dout => hourh);--时的低位
      u10: decoder port map( din => rdouth(7 downto 4),dout => hourl);--时的高位
      end Behavioral;