reg16b.vhd

基于Quartus II 5.0编写的正弦波发生器

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity reg16b is
	port( load:in std_logic;
		din: in std_logic_vector(15 downto 0);
		dout: out std_logic_vector(15 downto 0) );
end reg16b;

architecture behav of reg16b is
begin
	process(load,din)
	begin
	if load'event and load='1' then
	dout<=din;
	end if;
	end process;
end behav;