sin.vhd

来自「基于Quartus II 5.0编写的正弦波发生器」· VHDL 代码 · 共 39 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity sin is
port(
	clk : in std_logic;
	fword : in std_logic_vector(7 downto 0);
	dout : out std_logic_vector(7 downto 0)
	);
end  sin;

ARCHITECTURE one OF sin IS
	component data_rom
		port(address : in std_logic_vector(9 downto 0);
			clock : in std_logic;
			q : out std_logic_vector(7 downto 0) );
	end component;
	component reg16b 
	port( load:in std_logic;
		din: in std_logic_vector(15 downto 0);
		dout: out std_logic_vector(15 downto 0) );
	end component;
	component adder16b 
	port( a:in std_logic_vector(15 downto 0);
		b: in std_logic_vector(15 downto 0);
		s: out std_logic_vector(15 downto 0) );
	end component;
	signal f16b,d16b,din16b : std_logic_vector(15 downto 0);
	begin
	f16b(15 downto 14)<="00";
	f16b(13 downto 6)<=fword;
	f16b(5 downto 0)<="000000";
	u1 : adder16b port map (a=>f16b,b=>d16b,s=>din16b);
	u2 : reg16b port map (dout=>d16b,din=>din16b,load=>clk);
	u3 : data_rom port map (address=>d16b(15 downto 6),q=>dout,clock=>clk);	
end;