📄 suocunqi.txt
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library ieee;
use ieee.std_logic_1164.all;
entity suocunqi is
port(clr,clk,ena,oe:in std_logic;
d:in std_logic_vector(7 downto 0);
q:buffer std_logic_vector(7 downto 0));
end suocunqi;
architecture jiegou of suocunqi is
signal q_temp:std_logic_vector(7 downto 0);
begin
u1:process(clk,clr,ena,oe)
begin
if clr='0' then q_temp<="00000000";
elsif clk'event and clk='1'then
if (ena='1') then
q_temp<=d;
end if;
end if;
if oe='1' then q<="ZZZZZZZZ";
else q<=q_temp;
end if;
end process u1;
end jiegou;
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