代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/138605/13228643
txt vhdl.txt
5-1加法器(减法器电路设计
5-1-1全加器电路
--fadd.vhd fadd.vhd one bit full adder
library ieee ;
use ieee.std_logic_1164.all;
entity fadd is
port(
a: in std_logic;--被加数
b: in std_logic;---加数
ci : in std
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vhd freq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity freq is
port(fsin:in std_logic;
clk:in std_logic;
dout:out std_logic_vector(15 downto 0));
www.eeworm.com/read/138571/13231197
vhd fengpin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity fengpin is
port(
clk:in std_logic;
fpclk:out std_logic);
end fengpi
www.eeworm.com/read/240183/13232339
vhd synch_file.vhd
--synchronization time count
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity synch_file is
Port (synch:in std_logic;--synch
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vhd trace.vhd
--实现信号的输出
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity trace is
Port (judge1:in std_logic;
judge2:in std_logic;
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vhd temp.vhd
--屏蔽躁声信号
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity temp is
Port (temp_1 :in std_logic;
--temp_2 :in std_logic
www.eeworm.com/read/324566/13257549
txt vhdl-adder.txt
VHDL加法器
-- N-bit adder
-- The width of the adder is determined by generic N
library IEEE;
use IEEE.std_logic_1164.all;
entity adderN is
generic(N : integer := 16);
port (a :
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_info
m255
13
cModel Technology
dD:\system01\Sys01-X300-14jan04
Pcommonconstants
w1184639486
dC:\TDDOWNLOAD\cpudisgn\cpusample
FC:/TDDOWNLOAD/cpudisgn/cpusample/ram.vhd
l0
L1
VPLG@4;A7IZ5?oQA3BlMX^1
OE;C;6.
www.eeworm.com/read/324173/13280430
vhd cpld-0832.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dac is
port(wr,cs:out std_logic;
clk:in std_logic;
c_state:out st
www.eeworm.com/read/137697/13304054
vhd divd_fren.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity divd_fren is
port(
load:in std_logic;
clk_in:in std_log