fengpin.vhd

来自「此为用VHDL编写的可实现动感图像的点阵」· VHDL 代码 · 共 30 行

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_signed.all;
entity fengpin  is
      port(
            clk:in  std_logic;
                     fpclk:out std_logic);
end fengpin;
architecture   behavor  of  fengpin  is
    signal b:std_logic_vector(10 downto 0):="00000000000";
    begin
  process(clk)
  begin
  if(clk'event and clk='1') then
   b<=b+1;
  end if;
  fpclk<=b(10);
  end process;
  end behavor;