📄 divd_fren.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity divd_fren is
port(
load:in std_logic;
clk_in:in std_logic;
start:in std_logic;
stop: in std_logic;
data_in_h:in std_logic_vector(7 downto 0);
data_in_l:in std_logic_vector(7 downto 0);
clk_out:out std_logic
);
end divd_fren;
architecture a of divd_fren is
signal flag:std_logic=0;
signal temp_data_in_h:std_logic_vector(7 downto 0);
signal temp_data_in_l:std_logic_vector(7 downto 0);
signal temp_couter: std_logic_vector(7 downto 0);
signal temp_couter1: std_logic_vector(7 downto 0);
begin
process(clk_in,start,stop,load)
begin
--temp_couter<=temp_couter;
if(clk_in 'event and clk_in='1')then
if(stop='1')then
clk_out<='0';
else if(load='1')then
temp_data_in_h<=data_in_h;
temp_data_in_l<=data_in_l;
temp_couter<="00000000";
temp_couter1<="00000000";
end if;
end if;
if(start='1')then
if(flag='1')then
if(temp_couter/=temp_data_in_h)then
temp_couter<=temp_couter+1;
clk_out<='1';
flag<='1';
else
temp_couter<="00000000";
-- temp_couter<="00000000";
temp_couter1<="00000000";
flag<='0';
end if;
else
if(temp_couter1/=temp_data_in_l)then
temp_couter1<=temp_couter1+1;
clk_out<='0';
flag<='0';
else
temp_couter<="00000000";
temp_couter1<="00000000";
flag<='1';
end if;
end if;
end if;
end if;
--end if;
end process;
end a;
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