⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 synch_file.vhd

📁 EAS 的接收程序接收来自发射板的RF信号
💻 VHD
字号:
--synchronization time count
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity synch_file is 
 Port (synch:in std_logic;--synchronization time
       --temp_in_1:in  std_logic_vector(5 downto 0);
       --temp_in_2:in  std_logic_vector(5 downto 0);
       --temp_in_3:in  std_logic_vector(5 downto 0);
       timer :in std_logic;
       timer_begin:buffer std_logic_vector(2 downto 0);
       flat :buffer std_logic;                ---after synch
       control:out std_logic                --control to alarm
       --start:out std_logic;
       --temp_out_3:out std_logic;
      --end_timer: out std_logic
         ------
         --       count:out 
      );
end synch_file;
architecture behavioral of synch_file is
--signal flat:std_logic:='0';
signal temp:std_logic_vector(6 downto 0);
signal com :std_logic_vector(6 downto 0);

constant d1:std_logic_vector(6 downto 0):="0110100"; --52
constant d2:std_logic_vector(6 downto 0):="1000111";  --71

begin


--p1:process(synch)
--
--begin
process(synch)
begin
if synch'event and synch='1' then
 flat<=not flat;


end if;
--if falling_edge(synch) then
 --end_timer<='1';
--end if;
--if timer_begin="001" or timer_begin="010" or timer_begin="100" then
--end_timer<='0';


--end if;

end process;
process(flat)
variable count :std_logic_vector(1 downto 0);
begin
--wait until (rising_edge(flat));
if flat'event and flat='1' then
if count="11" then
 count:="00";
else
 count:=count+1;
end if;
if count="00"     then
  timer_begin<="001";
     elsif count="01"  then
  timer_begin<="010";
    elsif count="10"  then
  timer_begin<="100";
   else 
 NULL;
end if;
end if ;
--if flat'event and flat='1' then

end process;
process(timer)
begin
if timer'event and timer='1' then
if flat='1' then
temp<=temp+1;
else
temp<="0000000";
end if;
end if;
end process;


process(flat)
begin
if flat'event and flat='0' then
com<=temp;
end if;

end process;
process(com)
begin
if com>d1 and com<d2 then
control<='1';
else
control<='0';
end if;
end process;

end behavioral;

 

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -