freq.vhd

来自「实验四 频率计 实验要求：设计一个有效位为4位的十进制的数字频率计。」· VHDL 代码 · 共 34 行

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 

entity freq is 
port(fsin:in std_logic; 
     clk:in std_logic; 
     dout:out std_logic_vector(15 downto 0)); 
end freq; 

architecture testbody of freq is 
signal data:std_logic_vector(15 downto 0); 
begin 

process(clk) 
begin 
if rising_edge(clk) then 
dout<=data;
data<="0000000000000000";
end if; 
end process;

process(fsin) 
begin 
if rising_edge(fsin) then 
if data(11 downto 0)="100110011001" then data<=data+"011001100111"; 
elsif data(7 downto 0)="10011001" then data<=data+"01100111"; 
elsif data(3 downto 0)="1001" then data<=data+"0111"; 
else data<=data+'1'; 
end if; 
end if; 
end process; 

end testbody;