trace.vhd

EAS 的接收程序接收来自发射板的RF信号

--实现信号的输出
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity trace is 
 Port (judge1:in std_logic;
       judge2:in std_logic;
       judge3:in std_logic;
       timer:in std_logic;
       trace :in std_logic;
       green1:out std_logic;
       green2:out std_logic;
       green3:out std_logic;
       alarm:buffer std_logic
     );
end trace;
architecture behavioral of trace is
signal a :std_logic_vector(4 downto 0);
signal b :std_logic_vector(4 downto 0);
signal c :std_logic_vector(4 downto 0);
signal d :std_logic_vector(4 downto 0);
signal e :std_logic_vector(4 downto 0);
signal f :std_logic_vector(4 downto 0);

signal a_b :std_logic_vector(2 downto 0);
signal a_b1 :std_logic_vector(2 downto 0);
signal a_b2 :std_logic_vector(2 downto 0);
signal a_dy_b:std_logic;
signal a_dy_c:std_logic;
signal a_dy_d:std_logic;

constant c5:std_logic_vector(4 downto 0):="00101";   ---定义扫描数5
constant c10:std_logic_vector(4 downto 0):="01010";---定义扫描数10
constant c20:std_logic_vector(4 downto 0):="10100";---定义扫描数20

begin
process(timer,judge1,judge2,judge3)
variable count :std_logic_vector(15 downto 0):="0000000000000000";
variable count1 :std_logic_vector(4 downto 0):="00000";
variable count2 :std_logic_vector(4 downto 0):="00000";
variable count3 :std_logic_vector(4 downto 0):="00000";
variable green3_1:std_logic:='1';
variable green3_2:std_logic:='1';
variable green3_3:std_logic:='1';
variable link1:std_logic;
variable link2:std_logic;
variable link3:std_logic;


begin
-------------------------------------------信号算法
if timer'event and timer='1' then
if judge1='1' then
if trace='1' then
count1:=count1+1;
end if;
else 
a<=count1;
count1:="00000";
end if;
if judge2='1'then
if trace='1' then
count2:=count2+1;
end if;
else 
e<=count2;
count2:="00000";
end if;
if judge3='1'then
if trace='1' then
count3:=count3+1;
end if;
else 
f<=count3;
count3:="00000";
end if;
end if;

if a_b="100" then      --5
green1<='0';
elsif a_b="010" then   --10
green2<='0';
elsif a_b="001"  then  --20
green3_1:='0';
else 
NULL;
end if;

if a_b1="100" then      --5
green1<='0';
elsif a_b1="010" then   --10
green2<='0';
elsif a_b1="001"  then  --20
green3_2:='0';
else 
NULL;
end if;


if a_b2="100" then      --5
green1<='0';
elsif a_b2="010" then   --10
green2<='0';
elsif a_b2="001"  then  --20
green3_3:='0';
else 
NULL;
end if;







--------------------------------------------------------报警触发
if (green3_1='0'and green3_2='0' and green3_3='0') then
alarm<='0';
green3<='0';
end if;

------------------------------------------------------报警延时
if alarm='0' then
if count="1110101001100000" then  --3s
alarm<='1';
else
count:=count+1;
end if;
end if;
--end if;

end process;

---------------------------------------------------------比较器

process(a,e,f)   
variable a_dy_b1 :std_logic;
variable a_dy_c1 :std_logic;
variable a_dy_d1 :std_logic;
variable a_dy_b2 :std_logic;
variable a_dy_c2 :std_logic;
variable a_dy_d2 :std_logic;
begin
b<=c5;
c<=c10;
d<=c20;
if a>b then
a_dy_b<='1';
else
a_dy_b<= '0';
end if;
if a>c then
a_dy_c<='1';
else
a_dy_c<= '0';
end if;
if a>d then 
a_dy_d<='1'; 
else
a_dy_d<='0';
end if;
a_b<=a_dy_b & a_dy_c & a_dy_d;


if e>b then
a_dy_b1:='1';
else
a_dy_b1:= '0';
end if;
if e>c then
a_dy_c1:='1';
else
a_dy_c1:= '0';
end if;
if e>d then 
a_dy_d1:='1'; 
else
a_dy_d1:='0';
end if;
a_b1<=a_dy_b1 & a_dy_c1 & a_dy_d1;


if f>b then
a_dy_b2:='1';
else
a_dy_b2:= '0';
end if;
if f>c then
a_dy_c2:='1';
else
a_dy_c2:= '0';
end if;
if f>d then 
a_dy_d2:='1'; 
else
a_dy_d2:='0';
end if;
a_b2<=a_dy_b2 & a_dy_c2 & a_dy_d2;

end process;
end behavioral;