代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/327835/13059798

vhd clock.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY clock IS PORT(mode,adjust,clk2HZ,clk1HZ,reset,vcc:IN STD_LOGIC; en:OUT STD_LOGIC_VECTOR(0 TO 5); hh0,hh1,hh2,hh3,hh4,hh5,hh6:OUT STD_
www.eeworm.com/read/327835/13059817

vhd decode4_7.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decode4_7 IS PORT ( data: IN STD_LOGIC_VECTOR (3 DOWNTO 0); a,b,c,d,e,f,g: OUT STD_LOGIC); END decode4_7; ARCHITECTURE arc OF decode4_7 IS SI
www.eeworm.com/read/327830/13060409

vhd cout60.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cout60 IS PORT(en,clk: IN STD_LOGIC; qh,ql:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout:OUT STD_LOGIC );
www.eeworm.com/read/327830/13060505

vhd top.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY top IS PORT(mode,adjust,clk1,clks,clka,en,reset:IN STD_LOGIC; fout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
www.eeworm.com/read/327830/13060681

vhd cout60.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cout60 IS PORT(en,clk: IN STD_LOGIC; qh,ql:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout:OUT STD_LOGIC );
www.eeworm.com/read/327830/13060762

vhd top.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY top IS PORT(mode,adjust,clk1,clks,clka,en,reset:IN STD_LOGIC; fout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
www.eeworm.com/read/327450/13077312

vhd chw.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity chw is port(clk: in std_logic; q: out std_logic_vector(1 downto 0)); end chw; architecture ch
www.eeworm.com/read/327410/13080948

xml coregen.xml

www.eeworm.com/read/327323/13086991

vhd control_fsm_.vhd

------------------------------------------------------------------------------- -- -- -- X X XXXXXX XXXXXX
www.eeworm.com/read/326886/13111370

vhd portaout.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY portaout IS PORT( RESET : IN std_logic; CLK : IN std_logic; DIN : IN std_logic_vector (7 DOWNTO 0);