decode4_7.vhd

1．6个数码管静态显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、显示译码模块、顶层模块。要求使用实验箱右下角的6个

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decode4_7 IS
PORT ( data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a,b,c,d,e,f,g: OUT STD_LOGIC);
END decode4_7;
ARCHITECTURE arc OF decode4_7 IS
SIGNAL y:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
g<=y(0);
f<=y(1);
e<=y(2);
d<=y(3);
c<=y(4);
b<=y(5);
a<=y(6);
PROCESS(data)
BEGIN
case data is
when "0000"=> y<="0000001";
when "0001"=> y<="1001111";
when "0010"=> y<="0010010";
when "0011"=> y<="0000110";
when "0100"=> y<="1001100";
when "0101"=> y<="0100100";
when "0110"=> y<="0100000";
when "0111"=> y<="0001111";
when "1000"=> y<="0000000";
when "1001"=> y<="0000100";
when others=> y<="1111111";
end case;
END PROCESS;
END arc;