clock.vhd

1．6个数码管静态显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、显示译码模块、顶层模块。要求使用实验箱右下角的6个

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY clock IS
PORT(mode,adjust,clk2HZ,clk1HZ,reset,vcc:IN STD_LOGIC;
     en:OUT STD_LOGIC_VECTOR(0 TO 5);
     hh0,hh1,hh2,hh3,hh4,hh5,hh6:OUT STD_LOGIC;
     hl0,hl1,hl2,hl3,hl4,hl5,hl6,cout24:OUT STD_LOGIC;
     mh,ml,sh,sl:OUT STD_LOGIC_VECTOR(0 TO 3));
END clock;

ARCHITECTURE arc OF clock IS
COMPONENT mode_adjust
PORT (reset,mode,adjust,clk1HZ,clk2HZ:IN STD_LOGIC;
      clkh,clkm,clks,hin,min:OUT STD_LOGIC;
      en :OUT STD_LOGIC_VECTOR(0 TO 5) );
END COMPONENT;
COMPONENT count60
PORT ( 	clk ,en: IN STD_LOGIC;
		cout: 	OUT STD_LOGIC;
		hh,hl: 	OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT count24
PORT ( 	clk ,en: IN STD_LOGIC;
		cout: 	OUT STD_LOGIC;
		hh,hl: 	OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT decode4_7
PORT ( data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
       a,b,c,d,e,f,g: OUT STD_LOGIC);
END COMPONENT;

SIGNAL m_out,s_out:STD_LOGIC;
SIGNAL c_out:STD_LOGIC;
SIGNAL clkh,clkm,clks,hin,min:STD_LOGIC;
SIGNAL hh24,hl24:STD_LOGIC_VECTOR(0 TO 3);
SIGNAL mout,sout:STD_LOGIC;
BEGIN  
      mout<=hin OR( m_out AND s_out);cout24<=c_out;
      sout<=min OR s_out;
     G1:	mode_adjust PORT MAP(reset,mode,adjust,clk1HZ,clk2HZ,clkh,clkm,clks,hin,min,en);    
     G2:    count24 PORT MAP(clkh,mout,c_out,hh24,hl24);
     G3:    count60 PORT MAP(clkm,sout,m_out,mh,ml);
     G4:    count60 PORT MAP(clks,vcc,s_out,sh,sl);
     G5:    decode4_7 PORT MAP(hh24,hh0,hh1,hh2,hh3,hh4,hh5,hh6);
     G6:    decode4_7 PORT MAP(hl24,hl0,hl1,hl2,hl3,hl4,hl5,hl6);
END arc;