📄 cout60.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cout60 IS
PORT(en,clk: IN STD_LOGIC;
qh,ql:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout:OUT STD_LOGIC );
END cout60;
ARCHITECTURE arc OF cout60 IS
SIGNAL ah,al:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL a:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
qh<=ah;
ql<=al;
a<=ah&al;
PROCESS(en,clk)
BEGIN
IF(clk'EVENT AND clk='1')THEN
IF(en='1')THEN
CASE a IS
WHEN "00001001"|"00011001"|"00101001"|"00111001"|"01001001"=>
al<="0000";
ah<=ah+'1';
cout<='0';
WHEN "01011001"=>
ah<="0000";
al<="0000";
cout<='0';
WHEN "01011000"=>
al<=al+'1';
cout<='1';
WHEN OTHERS=>
al<=al+'1';
cout<='0';
END CASE;
END IF;
END IF;
END PROCESS;
END arc;
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