coregen.xml

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="memory" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
memory YourInstanceName (
    .addr(addr), // Bus [5 : 0] 
    .clk(clk),
    .din(din), // Bus [7 : 0] 
    .dout(dout), // Bus [7 : 0] 
    .en(en),
    .sinit(sinit),
    .we(we));

 
		</Template>
		<Template label="mem1" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
mem1 YourInstanceName (
    .addr(addr), // Bus [5 : 0] 
    .clk(clk),
    .din(din), // Bus [15 : 0] 
    .dout(dout), // Bus [15 : 0] 
    .en(en),
    .sinit(sinit),
    .we(we));

 
		</Template>
		<Template label="mem2" treetype="template">
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="memory" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component memory
    port (
    addr: IN std_logic_VECTOR(5 downto 0);
    clk: IN std_logic;
    din: IN std_logic_VECTOR(7 downto 0);
    dout: OUT std_logic_VECTOR(7 downto 0);
    en: IN std_logic;
    sinit: IN std_logic;
    we: IN std_logic);
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : memory
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            din =&gt; din,
            dout =&gt; dout,
            en =&gt; en,
            sinit =&gt; sinit,
            we =&gt; we);
 
		</Template>
		<Template label="mem1" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component mem1
    port (
    addr: IN std_logic_VECTOR(5 downto 0);
    clk: IN std_logic;
    din: IN std_logic_VECTOR(15 downto 0);
    dout: OUT std_logic_VECTOR(15 downto 0);
    en: IN std_logic;
    sinit: IN std_logic;
    we: IN std_logic);
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : mem1
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            din =&gt; din,
            dout =&gt; dout,
            en =&gt; en,
            sinit =&gt; sinit,
            we =&gt; we);
 
		</Template>
		<Template label="mem2" treetype="template">
		</Template>
	</Folder>
</RootFolder>