代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/454375/7392856
vhd segment7.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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www.eeworm.com/read/454372/7393004
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
entity rom is
port(
clk: in std_logic;
wave: out std_logic_vector(7 downto 0));
end rom;
library ieee;
library ieee;
use ieee.std_logic_11
www.eeworm.com/read/453834/7407279
vhd xianshi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port(cle,clk1,clk9,clk10,clear,set:in std_logic;
y:out std_logic_v
www.eeworm.com/read/453834/7407285
vhd baheyouxiji.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baheyouxiji is
port(bego,clk1,cp,left,right,clearhexin,clearxianshi:in std_logic;
www.eeworm.com/read/453834/7407293
vhd hexin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hexin is
port(bego,over,left,right,cp,clear:in std_logic;
www.eeworm.com/read/453834/7407305
vhd bahe.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bahe is
port(bego,left,right,cp,clear:in std_logic;--CP 接q18脚
q:inout std_logic_ve
www.eeworm.com/read/453834/7407346
vhd yima.vhd
library ieee;
use ieee.std_logic_1164.all;
entity yima is
port(a,b,c,d:in std_logic;
y: inout std_logic_vector(14 downto 0));
end yima;
architecture one of yima is
signal indat
www.eeworm.com/read/453834/7407349
vhd duolufuyong.vhd
library ieee;
use ieee.std_logic_1164.all;
entity duolufuyong is
port(sa,sb:in std_logic;
a,b:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0));
end duolufuy
www.eeworm.com/read/453834/7407614
vhd qiduanyima.vhd
library ieee;
use ieee.std_logic_1164.all;
entity qiduanyima is
port(a,b,c,d:in std_logic;
y:out std_logic_vector(6 downto 0));
end qiduanyima;
architecture one of qiduanyima is
www.eeworm.com/read/453698/7414041
vhd select_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity select_2 is
port(a,b,s:in std_logic;
q:out std_logic);
end;
architecture one of select_2 is
begin
q