select_2.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity select_2 is
port(a,b,s:in std_logic;
     q:out std_logic);
end;
architecture one of select_2 is
begin
q<=a when s='1' else b;
end;