duolufuyong.vhd

来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity duolufuyong is
port(sa,sb:in std_logic;
       a,b:in std_logic_vector(3 downto 0);
         q:out std_logic_vector(3 downto 0));
end duolufuyong;

architecture one of duolufuyong is
 begin
  process(sa,sb)
   begin
   if(sa='1')and(sb='0')then
     q(0)<=a(0);
     q(1)<=a(1);
     q(2)<=a(2);
     q(3)<=a(3);
   elsif(sb='1')and(sa='0')then
     q(0)<=b(0);
     q(1)<=b(1);
     q(2)<=b(2);
     q(3)<=b(3);
   end if;
  end process;
end one;