segment7.vhd

7段数码管译码器,用VHDL在FPGA2000上显示

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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entity segment7 is
   port(clk: in std_logic;
        sw17: in std_logic;
        sw: in std_logic_vector(3 downto 0);
        key3:in std_logic;
        hex0: out std_logic_vector(6 downto 0);
		hex1: out std_logic_vector(6 downto 0);
        led17: out std_logic);
   end segment7;
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architecture divide of segment7 is
signal count: std_logic_VECTOR(24 DOWNTO 0);
signal output: std_logic;
signal in1: std_logic_vector(3 downto 0):=sw;
signal out1: std_logic_vector(6 downto 0);
signal out2: std_logic_vector(6 downto 0);

begin
   process(clk,count)
 begin
      if (clk'event and clk='1') then
         count<=count+'1';
       end if;
		output<=count(24);
    end process;

   process(sw17,output,key3)
VARIABLE TEMP  : std_logic_vector(3 downto 0);
   begin
if (key3='0') then
	    if(sw17='0') then
        TEMP:="1111";
elsif (sw17='1')  then
TEMP:="0000";end if;
elsif (key3='1')then
		if(output'event and output='1') then
		if(sw17='0')then
		TEMP:=TEMP-'1';		
     elsif(sw17='1') then       
		TEMP:=TEMP+'1';
		end if;end if;
	
		
	end if;
	IN1<=TEMP;
	end process;
	process(in1)
begin	
	case in1 is
	when "0000" =>--0
		out1<="1000000";
		out2<="1000000";
	when "0001" =>--1
		out1<="1000000";
		out2<="1111001";
	when "0010" =>--2
		out1<="1000000";
		out2<="0100100";
	when "0011" =>--3
		out1<="1000000";
		out2<="0110000";
	when "0100" =>--4
		out1<="1000000";
		out2<="0011001";
	when "0101" =>--5
		out1<="1000000";
		out2<="0010010";
	when "0110" =>--6
		out1<="1000000";
		out2<="0000010";
	when "0111" =>--7
		out1<="1000000";
		out2<="1111000";
	when "1000" =>--8
		out1<="1000000";
		out2<="0000000";
	when "1001" =>--9
		out1<="1000000";
		out2<="0010000";
	when "1010" =>--10
		out1<="1111001";
		out2<="1000000";
	when "1011" =>--11
		out1<="1111001";
		out2<="1111001";
	when "1100" =>--12
		out1<="1111001";
		out2<="0100100";
	when "1101" =>--13
		out1<="1111001";
		out2<="0110000";
	when "1110" =>--14
		out1<="1111001";
		out2<="0011001";
	when "1111" =>--15
		out1<="1111001";
		out2<="0010010";
	when others => null;
end case;
end process;

	led17<=sw17;
	hex1<=out1;
	hex0<=out2;
end divide;
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